Publications

Books

Books: 3

2018

- Guilherme Arroz and José Monteiro and Arlindo L. Oliveira , Computer Architecture: Digital Circuits to Microprocessors , book, Oct. 2018, World Scientific [bibTex]

2007

- G. Arroz and José Monteiro and Arlindo L. Oliveira , Arquitectura de Computadores: dos Sistemas Digitais aos Microprocessadores , book, Jan. 2007, IST Press [bibTex]

1996

- José Monteiro and S. Devadas , Computer-Aided Design Techniques for Low Power Sequential Logic Circuits , book, Nov. 1996, Kluwer Academic Publishers [bibTex]

Book Chapters: 8

2016

- José Monteiro and R. Patel and V. Tiwari , Power Analysis and Optimization from Circuit to Register-Transfer Levels , chapter of EDA for IC Implementation, Circuit Design And Process Technology , Mar. 2016, CRC Press [bibTex]

2012

- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Multiplierless Design of Linear DSP Transforms , chapter of VLSI-SoC: Advanced Research for Systems on Chip , Jun. 2012, Springer [bibTex] [PDF]

2011

- António Gusmão and L. Miguel Silveira and José Monteiro , Power Macro-Modelling using an Iterative LS-SVM Method , chapter of VLSI-SoC: Technologies for Systems Integration , Jun. 2011, Springer [bibTex]

2009

- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Optimization Algorithms for Multiple Constant Multiplications , chapter of Advanced Topics in VLSI Design , Jan. 2009 [bibTex]

2008

- Rui Miguel Manteigas Cameira de Sousa e Rodrigues and José Monteiro , Review of the Algorithm Selection , chapter of Computational Intelligence: Methods and Applications , Jun. 2008, Exit Publishers [bibTex] [PDF]

2007

- L. Oliveira and Eduardo Costa and José Monteiro and J. Martins and S. Bampi and C. Santos and D. Ferrão and R. Reis , A Comparison of Layout Implementations of Pipelined And Non-Pipelined Signed Radix-4 Array Multiplier And Modified Booth Multiplier Architectures , chapter of VLSI-SoC: From Systems to Silicon , Sep. 2007, Springer [bibTex]

2006

- Eduardo Costa and José Monteiro and S. Bampi , Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths , chapter of VLSI-SOC: From Systems to Chips , May. 2006, Springer [bibTex]
- José Monteiro and V. Tiwari and P. Rakesh , Power Analysis and Optimization from Circuit to Register-Transfer Levels , chapter of EDA for IC Implementation, Circuit Design And Process Technology , Mar. 2006, CRC Press [bibTex]

Articles

International Journal Articles: 32

2022

- Leonardo L. de Oliveira and Gabriel H. Eisenkraemer and Everton A. Carara and João B. Martins and José Monteiro , Mobile Localization Techniques for Wireless Sensor Networks: Survey and Recommendations , article in , Sep. 2022, ACM [Article] [DOI Article link] [bibTex]
- Helena Alexandra Sabala Ruivo da Cruz and Mário Pereira Véstias and José Monteiro and Horácio C. Neto and Rui Policarpo Duarte , A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective , article in Remote Sensing vol. 14 (5) pp. 34 , Mar. 2022, MDPI [Article] [DOI Article link] [bibTex]
- Filipe Pedro Guerra Magalhães and José Monteiro and Juan Acebron and José Herrero Ramon , A Distributed Monte Carlo Based Linear Algebra Solver Applied to the Analysis of Large Complex Networks , article in Future Generation Computer Systems vol. 127 pp. 320-330 , Feb. 2022 [Article] [bibTex]

2020

- Ahmed Liacha and Abdelkrim K. Oudjida and Mohammed Bakiri and José Monteiro and Paulo Flores , Radix-2^r recoding with common subexpression elimination for multiple constant multiplication , article in IET Circuits Devices & Systems vol. 14 (7) pp. 990-994 , Oct. 2020 [DOI Article link] [bibTex]
- Juan Acebron and José Herrero and José Monteiro , A highly parallel algorithm for computing the action of a matrix exponential on a vector based on a multilevel Monte Carlo method , article in Computers and Mathematics with Applications vol. 79 (12) pp. 3495-3515 , Jun. 2020, Elsevier [DOI Article link] [bibTex]

2016

- Levent Aksoy and Paulo Flores and José Monteiro , A Novel Method for the Approximation of Multiplierless Constant Matrix Vector Multiplication , article in EURASIP Journal on Embedded Systems vol. 2016 (1) pp. 1-11 , May. 2016, Springer [DOI Article link] [bibTex]

2015

- Nuno P. Lopes and José Monteiro , Automatic Equivalence Checking of Programs With Uninterpreted Functions and Integer Arithmetic , article in International Journal on Software Tools for Technology Transfer (STTT) , Feb. 2015, Springer [bibTex]
- Diogo Brito and Taimur Rabuske and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and José Monteiro , Quaternary Logic Lookup Table in Standard CMOS , article in IEEE Transactions on Very Large Scale Integration Systems (TVLSI) vol. 23 (2) pp. 306–316 , Feb. 2015 [DOI Article link] [bibTex]
- Levent Aksoy and Paulo Flores and José Monteiro , Exact and Approximate Algorithms for the Filter Design Optimization Problem , article in IEEE Transactions on Signal Processing (TSP) vol. 63 (1) pp. 142-154 , Jan. 2015 [DOI Article link] [bibTex]

2014

- Levent Aksoy and Paulo Flores and José Monteiro , Multiplierless Design of Folded DSP Blocks , article in ACM Transactions on Design Automation of Electronic Systems (TODAES) vol. 20 (1) pp. 14:1-14:24 , Nov. 2014 [bibTex]
- Levent Aksoy and Paulo Flores and José Monteiro , A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures , article in Circuits, Systems and Signal Processing vol. 33 (6) pp. 1689-1719 , Jun. 2014, Springer [bibTex]

2013

- José Carlos Campos Costa and José Monteiro , Coverage-Directed Observability-Based Validation for Embedded Software , article in ACM Transactions on Design Automation of Electronic Systems (TODAES) vol. 18 (2) pp. 19:1-19:20 , Mar. 2013 [bibTex]
- Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and José Monteiro , Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool , article in IEEE Transactions on Very Large Scale Integration Systems (TVLSI) vol. 21 (3) pp. 498-511 , Mar. 2013 [bibTex] [PDF]
- João Bispo and João M. P. Cardoso and José Monteiro , Hardware Pipelining of Repetitive Patterns in Processor Instruction Traces , article in Journal of Integrated Circuits and Systems vol. 8 (1) pp. 22-31 , Mar. 2013 [bibTex]

2012

- Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and José Monteiro , High-Level Algorithms for the Optimization of Gate-Level Area in Digit-Serial Multiple Constant Multiplications , article in Integration, the VLSI Journal vol. 45 (3) pp. 294–306 , Jun. 2012, Elsevier [bibTex]
- Carlos Manuel Boura Sampaio and José Monteiro and L. Miguel Silveira , Analysis of the Conditions for the Worst Case Switching Activity in Integrated Circuits , article in Analog Integrated Circuits and Signal Processing vol. 70 (2) pp. 229-240 , Feb. 2012, Springer [bibTex]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Optimization Algorithms for the Multiplierless Realization of Linear Transforms , article in ACM Transactions on Design Automation of Electronic Systems (TODAES) vol. 17 (1) pp. 3:1-3:27 , Jan. 2012 [bibTex]

2011

- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Finding the Optimal Tradeoff Between Area and Delay in Multiple Constant Multiplications , article in Elsevier Journal on Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) vol. 35 (8) pp. 729-741 , Nov. 2011 [bibTex] [PDF]
- Cristiano Lazzari and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and José Monteiro , An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs , article in Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation vol. 6448 pp. 84-93 , Oct. 2011 [bibTex]
- Cristiano Lazzari and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and José Monteiro , Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays , article in Journal of Low Power Electronics vol. 7 (2) pp. 294-301 , Apr. 2011, American Scientific Publishers [bibTex]

2010

- L. Pieper and Eduardo Costa and S. Bampi and José Monteiro , Efficient Dedicated Multiplication Blocks for 2´s Complement Radix-16 and Radix-256 Array Multipliers , article in Journal of Computers vol. 5 (10) pp. 1502-1509 , Oct. 2010, Academy Publisher [bibTex]

2008

- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications , article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. 27 (6) pp. 1013 - 1026 , Jun. 2008, IEEE [DOI Article link] [bibTex]

2007

- Eduardo Costa and José Monteiro and S. Bampi , A New Regular Array Architecture for Signed Radix-2^m Multiplication , article in Integration: the VLSI Journal vol. 40 (2) pp. 118-132 , Jan. 2007, Elsevier Science Publishers [bibTex]

2004

- José Carlos Campos Costa and L. Miguel Silveira and Srinivas Devadas and José Monteiro , Power Estimation Using Probability Polynomials , article in Design Automation for Embedded Systems vol. 9 (1) pp. 19-52 , Mar. 2004, Spriger-Verlag [bibTex] [PDF]

2002

- José Monteiro and Arlindo L. Oliveira , Implicit FSM Decomposition Applied To Low Power Design , article in IEEE Transactions on Very Large Scale Integration Systems vol. 10 (5) pp. 560-565 , Oct. 2002, IEEE Press [Article] [DOI Article link] [bibTex] [PDF]

1998

- José Monteiro and S. Devadas , Power Estimation under User-Specified Input Sequences and Programs , article in Integrated Computer-Aided Engineering vol. 5 (2) pp. 177-185 , Oct. 1998, IOS Press [bibTex] [PDF]
- José Monteiro and Srinivas Devadas and Abhijit Ghosh , Sequential Logic Optimization for Low Power Using Input-Disabling Precomputation Architectures , article in IEEE Transactions on Computer-Aided Design vol. 17 (3) pp. 279-284 , Mar. 1998, IEEE Press [bibTex] [PDF]

1997

- José Monteiro and S. Devadas and A. Ghosh and K. Keutzer and J. White , Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation , article in IEEE Transactions on Computer-Aided Design vol. 16 (1) pp. 121-127 , Jan. 1997, IEEE Press [bibTex] [PDF]

1996

- José Monteiro and S. Devadas , Techniques for Power Estimation and Optimization at the Logic Level: A Survey , article in Journal of VLSI Signal Processing Systems vol. 13 (2) pp. 259-276 , Aug. 1996, Kluwer Academic Publishers [bibTex]
- José Monteiro and S. Devadas and A. Ghosh , Retiming Sequential Circuits for Low Power , article in International Journal of High Speed Electronics and Systems vol. 7 (2) pp. 323-340 , Jun. 1996, World Scientific Publishing [bibTex]

1995

- C-Y. Tsui and José Monteiro and M. Pedram and S. Devadas and A. Despain and B. Lin , Power Estimation Methods for Sequential Logic Circuits , article in IEEE Transactions on VLSI Systems vol. 3 (3) pp. 404-416 , Sep. 1995, IEEE Press [bibTex] [PDF]

1994

- M. Alidina and José Monteiro and S. Devadas and A. Ghosh and M. Papaefthymiou , Precomputation-Based Sequential Logic Optimization for Low Power , article in IEEE Transactions on VLSI Systems vol. 2 (2) pp. 426-436 , Dec. 1994, IEEE Press [bibTex] [PDF]

International Conferences: 102

2022

- O. Korakitis and S. Gonzalo and Nicolas Guidotti and João Barreto and José Monteiro and A. Peña , OmpSs-2 and OpenACC Interoperation , presented at Ninth Workshop on Accelerator Programming Using Directives , Nov. 2022 [bibTex]
- Orestis Korakitis and Simon Gonzalo and Nicolas Guidotti and João Barreto and José Monteiro and Antonio Peña , Towards OmpSs-2 and OpenACC Interoperation , presented at Symposium on Principles and Practice of Parallel Programming , Apr. 2022 [bibTex]

2021

- Nicolas Lee Guidotti and Pedro Maria de Lancastre e Távora Ceyrat and João Barreto and José Monteiro and Rodrigo Rodrigues and Ricardo Fonseca and X. Martorell and A. Peña , Particle-In-Cell Simulation using Asynchronous Tasking , presented at 27th International European Conference on Parallel and Distributed Computing (Euro-Par 21) , Aug. 2021 [bibTex]
- Roman Iakymchuk and Amândio Ribeiro Faustino and Andrew Emerson and João Barreto and Valeria Bartsch and Rodrigo Rodrigues and José Monteiro , Efficient and Eventually Consistent Collective Operations , presented at IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW) , Jun. 2021 [DOI Article link] [bibTex]

2020

- Rafael Santos and João Pedro Afonso and José Monteiro , Short-circuit Analysis using a Parallel QBF Solver , presented at XXXV Conference on Design of Circuits and Integrated Systems (DCIS 2020) , Nov. 2020 [bibTex]

2017

- Liacha Ahmed and A. Oudjida and José Monteiro and Paulo Flores , A variable RADIX-2r algorithm for single constant multiplication , presented at 15th IEEE International New Circuits and Systems Conference (NEWCAS , Jun. 2017 [bibTex]
- João Pedro Afonso and José Monteiro , Analysis of Short-Circuit Conditions in Logic Circuits , presented at IEEE/ACM Design, Automation and Test in Europe (DATE) , Mar. 2017 [bibTex]

2015

- Levent Aksoy and Paulo Flores and José Monteiro , A Novel Method for the Approximation of Multiplierless Constant Matrix Vector Multiplication , presented at 13th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC) - Best Paper Award , Oct. 2015 [bibTex]
- Levent Aksoy and Paulo Flores and José Monteiro , Approximation of multiple constant multiplications using minimum look-up tables on FPGA , presented at IEEE International Symposium on Circuits and Systems (ISCAS) , May. 2015 [bibTex]

2014

- Levent Aksoy and Paulo Flores and José Monteiro , Efficient Design of FIR Filters Using Hybrid Multiple Constant Multiplications on FPGA , presented at IEEE International Conference on Computer Design (ICCD) , Oct. 2014 [bibTex]
- Levent Aksoy and Paulo Flores and José Monteiro , ECHO: A Novel Method for the Multiplierless Design of Constant Array Vector Multiplication , presented at IEEE International Symposium on Circuits and Systems (ISCAS) , Jun. 2014 [bibTex]
- Levent Aksoy and Paulo Flores and José Monteiro , On the multiplierless design of correctly rounded multiple constant divisions , presented at IEEE/ACM International Workshop on Logic Synthesis (IWLS) , May. 2014 [bibTex]
- Levent Aksoy and Paulo Flores and José Monteiro , Optimization of Design Complexity in Time-Multiplexed Constant Multiplications , presented at Design, Automation and Test in Europe DATE) , Mar. 2014 [bibTex]
- Nuno P. Lopes and José Monteiro , Weakest Precondition Synthesis for Compiler Optimizations , presented at 15th International Conference on Verification, Model Checking, and Abstract Interpretation (VMCAI) , Jan. 2014 [bibTex]

2013

- Levent Aksoy and Paulo Flores and José Monteiro , Towards the Least Complex Time-Multiplexed Constant Multiplication , presented at 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) , Oct. 2013 [bibTex] [PDF]
- L. Pieper and Eduardo Costa and José Monteiro , Combination of Radix-2^m Multiplier Blocks and Adder Compressors for the Design of Efficient 2's Complement 64-bit Array Multipliers , presented at 26th Symposium on Integrated Circuits and System Design , Sep. 2013 [bibTex]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Exploration of Tradeoffs in the Design of Integer Cosine Transforms for Image Compression , presented at 21st European Conference on Circuit Theory and Design (ECCTD) , Sep. 2013 [bibTex] [PDF]
- Nuno P. Lopes and José Monteiro , Automatic Equivalence Checking of UF+IA Programs , presented at International SPIN Symposium on Model Checking of Software - SPIN13 , Jul. 2013 [bibTex]
- Diogo Brito and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and José Monteiro , Standard CMOS Voltage-Mode QLUT Using a Clock Boosting Technique , presented at 11th IEEE International NEWCAS Conference , Jun. 2013 [bibTex]
- Levent Aksoy and Paulo Flores and José Monteiro , SIREN: A Depth-First Algorithm for the Filter Design Optimization Problem , presented at Great Lakes Symposium on VLSI (GLSVLSI) , May. 2013 [bibTex] [PDF]

2012

- Diogo Brito and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and José Monteiro , Design and Characterization of a QLUT in a Standard CMOS Process , presented at IEEE International Conference on Electronics, Circuits, and Systems (ICECS) , Dec. 2012 [bibTex]
- S. Ghissoni and Eduardo Costa and José Monteiro and R. Reis , Efficient Area and Power Multiplication Part of FFT Based on Twiddle Factor Decomposition , presented at 19th IEEE International Conference on Electronics, Circuits and Systems – ICECS2012 , Dec. 2012 [bibTex]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Multiple Tunable Constant Multiplications: Algorithms and Applications , presented at International Conference on Computer-Aided Design (ICCAD) , Nov. 2012 [bibTex] [PDF]
- João Bispo and João Cardoso and José Monteiro , Hardware Pipelining of Runtime-Detected Loops , presented at IEEE XXV Symposium on Integrated Circuits and Systems Design (SBCCI) , Sep. 2012 [bibTex]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs , presented at Design Automation and Test in Europe (DATE) , Mar. 2012 [bibTex] [PDF]

2011

- S. Ghissoni and Eduardo Costa and José Monteiro and R. Reis , Combination of Constant Matrix Multiplication and Gate-level Approaches for Area and Power Efficient Hybrid Radix-2 DIT FFT Realization , presented at 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , Dec. 2011 [bibTex]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , A Hybrid Algorithm for the Optimization of Area and Delay in Linear DSP Transforms , presented at IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) , Oct. 2011 [bibTex] [PDF]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Optimization of Gate-Level Area in High Throughput Multiple Constant Multiplications , presented at European Conference on Circuit Theory and Design (ECCTD) , Aug. 2011 [bibTex] [PDF]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Design of Low-Power Multiple Constant Multiplications Using Low-Complexity Minimum Depth Operations , presented at Great Lakes Symposium on VLSI (GLSVLSI) , May. 2011 [bibTex] [PDF]
- Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and José Monteiro , Efficient Shift-Adds Design of Digit-Serial Multiple Constant Multiplications , presented at Great Lakes Symposium on VLSI (GLSVLSI) , May. 2011 [bibTex] [PDF]
- L. Oliveira and G. Dessbesell and J. Martins and José Monteiro , Hardware Implementation of a Centroid-based Localization Algorithm for Mobile Sensor Networks , presented at IEEE International Symposium on Circuits and Systems (ISCAS) , May. 2011 [bibTex]
- Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and José Monteiro , Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level , presented at IEEE International Symposium on Circuits and Systems (ISCAS) , May. 2011 [bibTex] [PDF]

2010

- S. Ghissoni and Eduardo Costa and Cristiano Lazzari and José Monteiro and Levent Aksoy and R. Reis , Radix-2 Decimation in Time (DIT) Implementation Based on a Matrix-Multiple Constant Multiplication Approach , presented at 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) , Dec. 2010 [bibTex]
- Cristiano Lazzari and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and José Monteiro , An Efficient Low Power Multiple-Value Look-up Table Targeting Quaternary FPGAs , presented at International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS’10) , Sep. 2010 [bibTex]
- L. Oliveira and G. Dessbesell and J. Martins and José Monteiro , CentroidM: a Centroid-based Localization Algorithm for Mobile Sensor Networks , presented at IEEE XXIII Symposium on Integrated Circuits and Systems Design (SBCCI) , Sep. 2010 [bibTex]
- Diego Jaccottet and Eduardo Costa and Levent Aksoy and Paulo Flores and José Monteiro , Design of Low-Complexity and High-Speed Digital Finite Impulse Response Filters , presented at International Conference on VLSI and System on Chip (VLSI-SoC) , Sep. 2010 [bibTex] [PDF]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications , presented at Euromicro Conference on Digital System Design , Aug. 2010 [bibTex] [PDF]
- Cristiano Lazzari and Paulo Flores and José Monteiro and Luigi Carro , Voltage-mode Quaternary FPGAs: An Evaluation of Interconnections , presented at IEEE International Symposium on Circuits and Systems (ISCAS 2010) , May. 2010 [bibTex] [PDF]
- Cristiano Lazzari and Paulo Flores and José Monteiro and Luigi Carro , A New Quaternary FPGA Based on a Voltage-mode Multi-valued Circuits , presented at Design, Automation & Test in Europe (DATE 2010) , Mar. 2010 [bibTex] [PDF]
- Carlos Manuel Boura Sampaio and José Monteiro and L. Miguel Silveira , Analysis of the Conditions for Worst Case Switching Activity in Integrated Circuits , presented at IEEE Latin American Symposium on Circuits and Systems (LASCAS) , Feb. 2010 [bibTex]

2009

- Cristiano Lazzari and Paulo Flores and José Monteiro , Power and Delay Comparison of Binary and Quaternary Arithmetic Circuits , presented at IEEE International Conference on Signals, Circuits and Systems (SCS’09) , Nov. 2009 [DOI Article link] [bibTex] [PDF]
- José Carlos Campos Costa and José Monteiro , Observability-based Coverage-directed Path Search using PBO for Automatic Test Vector Generation , presented at IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) , Oct. 2009 [bibTex] [PDF]
- António Gusmão and L. Miguel Silveira and José Monteiro , Power Macro-Modelling using an Iterative LS-SVM Method , presented at IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) , Oct. 2009 [bibTex] [PDF]
- S. Ghissoni and J. Martins and R. Reis and José Monteiro , Analysis of Power Consumption using a New Methodology for the Capacitance Modeling of Complex Logic Gates , presented at International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) , Sep. 2009 [bibTex]
- José Carlos Campos Costa and José Monteiro , A MILP-based Approach to Path Sensitization of Embedded Software , presented at IEEE Design, Automation and Test in Europe (DATE) , Apr. 2009 [bibTex] [PDF]
- António Gusmão and L. Miguel Silveira and José Monteiro , Parameter Tuning in SVM-Based Power Macro-Modeling , presented at IEEE International Symposium on Quality Electronic Design (ISQED) , Mar. 2009 [DOI Article link] [bibTex] [PDF]

2008

- L. Pieper and Eduardo Costa and S. Bampi and José Monteiro , Efficient Dedicated Multiplication Blocks for 2´s Complement Radix-16 and Radix-256 Array Multipliers , presented at International Conference on Signals, Circuits & Systems (SCS08) , Nov. 2008 [bibTex] [PDF]
- P. Marques Morgado and Paulo Flores and José Monteiro and L. Miguel Silveira , Generating Worst-case Stimuli for Accurate Power Grid Analysis , presented at International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) , Sep. 2008 [bibTex] [PDF]
- José Carlos Campos Costa and José Monteiro , Computation of the Minimal Set of Paths for Observability-Based Statement Coverage , presented at 15th International Conference Mixed Design of Integrated Circuits and Systems , Jun. 2008 [bibTex] [PDF]
- Rui Miguel Manteigas Cameira de Sousa e Rodrigues and José Monteiro , Review of the Algorithm Selection , presented at Eighth International Conference on Artificial Intelligence and Soft Computing , Jun. 2008 [bibTex] [PDF]
- L. Pieper and Eduardo Costa and S. Almeida and S. Bampi and José Monteiro , Efficient Dedicated Structures for the Radix-16 Multiplication , presented at XIV Iberchip , Feb. 2008 [bibTex] [PDF]

2007

- Levent Aksoy and Eduardo Costa and Ece Gunes and Paulo Flores and José Monteiro , Effect of Number Representation on the Achievable Minimum Number of Operations , presented at IEEE Workshop on Signal Processing Systems (SiPS) , Oct. 2007 [bibTex] [PDF]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Minimum Number of Operations under a General Number Representation for Digital Filter Synthesis , presented at Proceedings of the European Conference on Circuit Theory and Design (ECCTD) , Aug. 2007 [bibTex] [PDF]
- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , Optimization of Area in Digital FIR Filters using Gate-Level Metrics , presented at IEEE/ACM Design Automation Conference (DAC) , Jun. 2007 [bibTex] [PDF]
- Rudolfo Santos and José Monteiro , Foot Fingerprints , presented at IADIS International Conference on Applied Computing , Feb. 2007 [bibTex] [PDF]

2006

- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis , presented at IEEE International Conference on Electronics, Circuits and Systems (ICECS) , Dec. 2006 [bibTex] [PDF]
- Eduardo Costa and Paulo Flores and José Monteiro , Exploiting General Coefficient Representation for the Optimal Exploiting Sharing of Partial Products in MCMs , presented at IEEE XIX Symposium on Integrated Circuits and Systems Design , Aug. 2006 [bibTex] [PDF]

2005

- Paulo Flores and José Monteiro and Eduardo Costa , An Exact Algorithm for the Maximal Sharing of Partial Terms in Multiple Constant Multiplications , presented at International Conference on Computed Aided Design (ICCAD) , Nov. 2005 [bibTex] [PDF]
- José Monteiro and Jorge Manuel dos Santos Ribeiro Fernandes and L. Miguel Silveira , A Case for a Triangular Waveform Clock Signal , presented at VLSI-SoC'2005 - IFIP International Conference on Very Large Scale Integration , Oct. 2005 [bibTex] [PDF]
- L. Oliveira and C. Santos and D. Ferrão and E. Costa and José Monteiro and J. Martins and S. Bampi and R. Reis , A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures , presented at VLSI-SoC'2005 - IFIP International Conference on Very Large Scale Integration , Oct. 2005 [bibTex] [PDF]
- M. Fonseca and E. Costa and S. Bampi and José Monteiro , Design of a Radix-2^n Hybrid Array Multiplier Using Carry Save Adders , presented at IEEE XVIII Symposium on Integrated Circuits and Systems Design , Sep. 2005 [bibTex] [PDF]
- Eduardo Costa and Paulo Flores and José Monteiro , Maximal Sharing of Partial Terms in MCM under Minimal Signed Digit Representation , presented at European Conference on Circuit Theory and Design (ECCTD) , Sep. 2005 [bibTex] [PDF]
- V. Rosa and S. Bampi and E. Costa and José Monteiro , Performance Evaluation of Parallel FIR Filter Optimizations in ASICs and FPGA , presented at IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2005) , Aug. 2005 [bibTex] [PDF]
- M. Fonseca and E. Costa and S. Bampi and José Monteiro , Performance Optimization of Radix-2^n Multipliers using Carry Save Adders , presented at Iberchip , Mar. 2005 [bibTex] [PDF]

2004

- V. Rosa and E. Costa and S. Bampi and José Monteiro , An Improved Synthesis Method for Low Power Hardwired FIR Filters , presented at XVII Symposium on Integrated Circuits and Systems Design , Sep. 2004 [bibTex] [PDF]
- L. Oliveira and E. Costa and S. Bampi and J. Martins and José Monteiro , Array Hybrid Multiplier versus Modified Booth Multiplier: Comparing Area and Power Consumption of Layout Implementations , presented at IEEE International Midwest Symposium on Circuits and Systems , Jul. 2004 [bibTex] [PDF]

2003

- E. Costa and S. Bampi and José Monteiro , Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths , presented at IFIP VLSI-SOC , Dec. 2003 [bibTex] [PDF]
- E. Costa and S. Bampi and José Monteiro , Low Power Architectures for FFT and FIR Dedicated Datapaths , presented at IEEE Midwest Symposium on Circuits & Systems , Dec. 2003 [bibTex] [PDF]
- José Carlos Campos Costa and José Monteiro , Input Generation for Path Coverage in Software Testing , presented at IEEE Workshop on Compilers and Tools for Constrained Embedded Systems , Oct. 2003 [bibTex] [PDF]
- E. Costa and S. Bampi and José Monteiro , A New Pipelined Array Architecture for Signed Multiplication , presented at IEEE XVI Symposium on Integrated Circuits and Systems Design , Sep. 2003 [bibTex] [PDF]
- J. Portela and E. Costa and José Monteiro , Optimal Combination of Number of Taps and Coefficient Bit-Width for Low Power FIR Filter Realization , presented at IEEE European Conference on Circuit Theory and Design , Sep. 2003 [bibTex] [PDF]

2002

- E. Costa and S. Bampi and José Monteiro , A New Architecture for 2's Complement Gray Encoded Array Multiplier , presented at IEEE XV Symposium on Integrated Circuits and Systems Design , Sep. 2002 [bibTex] [PDF]
- E. Costa and S. Bampi and José Monteiro , A New Architecture for Signed Radix-2^m Pure Array Multipliers , presented at IEEE International Conference on Computer Design , Sep. 2002 [bibTex] [PDF]
- E. Costa and S. Bampi and José Monteiro , FIR Filter Design using Low Power Arithmetic Operators , presented at IEEE Design and Diagnostics of Electronic Circuits and Systems , Apr. 2002 [bibTex] [PDF]

2001

- E. Costa and S. Bampi and José Monteiro , Power Efficient Arithmetic Operand Encoding , presented at XIV Symposium on Integrated Circuits and Systems Design , Sep. 2001 [bibTex] [PDF]
- J. Portela and José Monteiro , Power Optimized Viterbi Decoder Implementation through Architectural Transforms , presented at XIV Symposium on Integrated Circuits and Systems Design , Sep. 2001 [bibTex] [PDF]
- Eduardo César da Costa and Ségio Bampi and José Monteiro , Power Optimization Using Coding Methods on Arithmetic Operators , presented at IEEE International Symposium on Signals, Circuits and Systems , Jul. 2001 [bibTex] [PDF]

2000

- José Carlos Campos Costa and S. Devadas and José Monteiro , Observability Analysis for Embedded Software in a Coverage-Directed Validation Methodology , presented at IEEE/ACM International Conference on Computer-Aided Design , Nov. 2000 [bibTex] [PDF]
- J. Baptista and R. Reis and José Monteiro , Capacitance and Power Modeling at the Logic Level , presented at IFIP International Conference on Chip Design Automation , Aug. 2000 [bibTex] [PDF]
- R. Ferreira and A. M. Trullemans and José Carlos Campos Costa and José Monteiro , Probabilistic Bottom-up RTL Power Estimation , presented at IEEE/ACM International Symposium on Quality of Electronic Design , Mar. 2000 [bibTex] [PDF]
- José Monteiro and Arlindo L. Oliveira , FSM Decomposition by Direct Circuit Manipulation Applied to Low Power Design , presented at IEEE/ACM Asian and South Pacific Design Automation Conference , Jan. 2000 [bibTex] [PDF]

1999

- A. S. Mota and N. M. Ferreira and Arlindo L. Oliveira and José Monteiro , Integrating Dynamic Power Management in the Design Flow , presented at X IFIP Conference on VLSI , Dec. 1999 [bibTex] [PDF]
- Ana T. Freitas and Arlindo L. Oliveira and José Monteiro and Horácio C. Neto , Exact Power Estimation Using Word Level Transition Probabilities , presented at IEEE International Workshop on Power and Timing Modelling, Optimization and Simulation , Oct. 1999 [bibTex] [PDF]
- José Carlos Campos Costa and José Monteiro and L. Miguel Silveira and S. Devadas , A Probabilistic Approach for RT-Level Power Modeling , presented at IEEE International Conference on Electronics, Circuits and Systems , Sep. 1999 [bibTex] [PDF]
- José Monteiro , Power Optimization using Dynamic Power Management , presented at XII Symposium on Integrated Circuits and Systems Design , Sep. 1999 [bibTex] [PDF]
- José Carlos Campos Costa and L. Miguel Silveira and José Monteiro , Sequential Power Estimation using Probability Polynomials , presented at IEEE International Symposium on Signals, Circuits and Systems, , Jul. 1999 [bibTex] [PDF]

1998

- José Monteiro , Techniques for Power Management at the Logic Level , presented at IEEE International Conference on Electronics, Circuits and Systems , Sep. 1998 [bibTex] [PDF]
- José Monteiro and Arlindo L. Oliveira , Finite State Machine Decomposition for Low Power , presented at ACM/IEEE Design Automation Conference , Jun. 1998 [bibTex] [PDF]
- A. S. Mota and José Monteiro and Arlindo L. Oliveira , Power Optimization of Combinational Modules using Self-timed Precomputation , presented at IEEE International Symposium on Circuits and Systems , May. 1998 [bibTex] [PDF]

1997

- José Carlos Campos Costa and José Monteiro and S. Devadas , Switching Activity Estimation using Limited Depth Reconvergent Path Analysis , presented at IEEE/ACM International Symposium on Low Power Electronics and Design , Aug. 1997 [bibTex] [PDF]
- José Monteiro and Joao Marques Silva , Testability Analysis of Circuits using Data-Dependent Power Management , presented at IX IFIP International Conference on Very Large Scale Integration , Aug. 1997 [bibTex] [PDF]
- Joao Marques Silva and José Monteiro and K. Sakallah , Test Pattern Generation for Circuits Using Power Management Techniques , presented at IEEE European Test Workshop , May. 1997 [bibTex] [PDF]

1996

- José Monteiro and S. Devadas and P. Ashar and A. Mauskar , Scheduling Techniques to Enable Power Management , presented at IEEE/ACM 33rd Design Automation Conference , Jun. 1996 [bibTex] [PDF]

1995

- José Monteiro and S. Devadas , Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs , presented at IEEE/ACM International Symposium on Low Power Electronics and Design , Apr. 1995 [bibTex] [PDF]
- José Monteiro and J. Rinderknecht and S. Devadas and A. Ghosh , Optimization of Combinational and Sequential Logic Circuits for Low Power Using Precomputation , presented at Chapel Hill Conference on Advanced Research in VLSI , Mar. 1995 [bibTex] [PDF]

1994

- M. Alidina and José Monteiro and S. Devadas and A. Ghosh and M. Papaefthymiou , Precomputation-Based Sequential Logic Optimization for Low Power , presented at IEEE/ACM International Conference on Computer-Aided Design , Nov. 1994 [bibTex] [PDF]
- José Monteiro and S. Devadas and B. Lin , A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits , presented at IEEE/ACM 31st Design Automation Conference , Jun. 1994 [bibTex] [PDF]
- José Monteiro and J. Kukula and S. Devadas and Horácio C. Neto , Bitwise Encoding of Finite State Machines , presented at IEEE 7th International Conference on VLSI Design , Jan. 1994 [bibTex] [PDF]

1993

- José Monteiro and S. Devadas and A. Ghosh , Retiming Sequential Circuits for Low Power , presented at IEEE/ACM International Conference on Computer-Aided Design , Nov. 1993 [bibTex] [PDF]

National Conferences: 3

2021

- Miguel Soares Marques and José Monteiro and Rodrigo Rodrigues and João Barreto , Rethinking Linux's Page Management to Support the new Intel Optane DC Persistent Memory , presented at Inforum , Sep. 2021 [bibTex]

2020

- Dinis Pedro Pinto Marcos Madeira and José Monteiro and Rui Policarpo Duarte , Specification and Implementation of the Didactic Processor P4 and Its Development Environment , presented at XVI Jornadas Sobre Sistemas Reconfiguráveis (REC 2020) , Feb. 2020 [bibTex]

2008

- L. Pieper and Eduardo Costa and S. Almeida and S. Bampi and José Monteiro , New Dedicated Architectures for the Radix-16 Multiplication , presented at 23rd South Symposium on Microelectronics , May. 2008 [bibTex]

Dissertations

PhD Theses: 1

1996

- José Monteiro advised by Srinivas Devadas , A Computer-Aided Design Methodology for Low Power Sequential Logic Circuits , PhD Thesis at Massachusetts Institute of Technology (before Bolonha), May. 1996 [bibTex] [PDF]

MSc Theses: 1

1993

- José Monteiro advised by Horácio C. Neto , Codificação de Máquinas de Estados na Síntese Automática de Circuitos Lógicos , MSc Thesis at Instituto Superior Técnico (before Bolonha), Jan. 1993 [bibTex]

as Editors

Edited Books: 3

2019

- M. Maniatakos and I. Elfadel and M. Reorda and H. Ugurdag and José Monteiro and R. Reis , editors, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things , Jan. 2019, Springer [bibTex]

2010

- José Monteiro and R. van Leuken , editors, Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation , Lecture Notes in Computer Science 5953, Feb. 2010, Springer [bibTex]

2009

- L. Svensson and José Monteiro , editors, Integrated Circuit and System Design: Power and Timing Modeling Optimization and Simulation , Lecture Notes in Computer Science 5349, Feb. 2009, Springer [bibTex]

Other Publications: 1

2012

- Levent Aksoy and Eduardo Costa and Paulo Flores and José Monteiro , editors, Multicon - Multiplierless Design of Low-Complexity and High-Speed DSP Systems , Mar. 2012, Poster at University Booth: Se [bibTex]

Special Issues of Journals (editor): 1

2010

- José Monteiro , editor, , Journal of Low Power Electronics , Apr. 2010 [bibTex]

Technologies

National Patents: 1

2010

- Jorge Manuel dos Santos Ribeiro Fernandes and Cristiano Lazzari and Paulo Flores and José Monteiro , Tabela Multi-Valor para Dispositivos Lógicos Programáveis , Sep. 2010, Pedido Provisório de Patente - INPI [bibTex]

Reports

Technical Reports: 3

2010

2005

2000

- José Monteiro and A. Mota , PCBIT Final Report , INESC-ID Tec. Rep. 3/2000 , Feb. 2000 [bibTex]