Microprocessor Model

The microprocessor is the development which has given rise to the ubiquitous computing we see today. With the advent of LSI and VLSI, sophisticated processors, I/O devices, and memory are now available in cheap, convenient, readily available chips. For a couple of dollars, you can buy a processor significantly more powerful than the PDP-8. You can even get single-chip computers (processor, RAM, ROM, and I/O ports are all on one chip) that even include high level language interpreters built-in for a pittance.

Memory Access

Typically, a microprocessor provides an address bus and a data bus to the outside world. The address bus is usually a write-only bus (from the point of view of the processor), where the data bus is bi- directional. When the processor wants to read a word from memory, it asserts the address of the desired word, signals to the memory system that it wants to read, and then checks for the data on the data bus. It is the responsibility of the memory to assert the data on the data bus. Also, it is the responsibility of the memory to either tell the processor when data is available on the data bus or be certain the data is available within a set amount of time.

Note that there can be many memory devices in a microprocessor based computer. There can be several RAM chips and a couple of ROM chips. All share the data bus and must be told when they can write to it. Each chip therefore has an address recognizer associated with it which tells the chip when it needs to worry about reads or writes.

I/O Access

I/O access in the microprocessor world is divided into two camps.

Memory Mapped: In this model, registers in I/O devices are arranged in the memory map like memory cells. To read or write from a device, the processor uses the usual memory read and write opcodes. This model has the advantage of simplicity. It has the disadvantage that it divides up the memory map.
Separate I/O: Here, memory is in one map; and there is another map for I/O devices. There are separate commands for accessing memory and accessing I/O. The processor will assert signals to the outside world to tell the attached devices whether it is doing a memory access or an I/O access. This is a more complex approach than memory mapped I/O, but it leaves the memory map less cluttered (in theory) and simplifies address recognition.

Designer's Model

There are a number of models of 6809 (some even have built-in RAM, ROM, and even I/O ports). The version we will be working with is the MC6809B---the 2 MHz version of the plain vanilla 6809. The chip comes in a 40 pin package (either ceramic or plastic). The pins come in a number of different groups:

A15-A0

These are the address lines of the 6809. The address for a memory cell to read or write is asserted on these lines. They are strictly outputs from the 6809 (although they often go into Hi-Z).

D7-D0

These are the bi-directional lines for getting data into or out of the 6809. On a read, the 6809 expects the memory or peripherals to assert a value here. On a write, it expects everyone to stay quiet, and it will do the writing.

R/W

This line indicates what kind of operation the 6809 wants to do. If the line is high, the 6809 is reading from memory or I/O. If it is low, the 6809 is writing to memory or I/O.

Q & E

These are the clocks generated by the 6809 to govern timing of the rest of the machine. When Q rises, the address lines are stable. When E rises, the data lines are stable (if the 6809 is writing). When E falls, the 6809 latches the data on the data lines (if the 6809 is reading). Note that Q leads E by a quarter wave. Q and E Clocks

DMA/BREQ

The 6809 provides for Direct Memory Access for peripherals. If a peripheral wants to access memory directly for a burst transfer, it pulls this line low. The 6809 will eventually grant the request and will refrain from controlling the address bus for as long as the DMA input is low. The 6809 has limited patience, however... all the peripheral gets is 15 clock cycles.

BA & BS

These two signals provide some useful information about what the processor is doing and what the status of the address bus is. Here is a summary:

BA	BS	Status
0	0	Running
0	1	Processing interrupt or RESET
1	0	Waiting in a SYNC
1	1	DMA granted, or processor halted

Note that, when BA is high, the address lines will not be driven by the 6809. If no other device provides values for them, they will float. Watch out for this!

MRDY

This line indicates whether or not the memory system is ready to return data to the processor; it is only useful for slower memory or I/O devices. If memory is ready, it should make sure that MRDY is high. If MRDY is low, the 6809 will extend Q and E to give the memory some time.

XTAL & EXTAL

These two inputs are used to generate the Q and E clock signals. For a 6809B, you should either tie a 4 MHz crystal between these lines or connect XTAL to ground and EXTAL to the output of a 4 MHz oscillator. This signal is divided to generate Q and E.

HALT

A low input on this pin halts the 6809. No interrupts will be processed, but DMA will be acknowledged.

RESET

A low on this pin will trigger a processor reset. The 6809 will fetch the word stored at $FFFE and $FFFF. This word is the address of the code to start running.

NMI, FIRQ, & IRQ

These inputs trigger interrupt processing. The interrupts are triggered by a low going edge.

VSS & VCC

These are ground and power, respectively. Note that they are not in the usual locations.

Programmer's Model

Registers

There are five 16-bit registers: X, Y, U, S, and PC. All of the 16-bit registers are considered to be pointers in that they are used to point into memory. There are four 8-bit registers: A, B, DP, and CC.

X, and Y are considered to be index registers. They are used as pointers into memory and are used in a variety of addressing modes (to be described below).

U and S are the stack pointers. Unlike other microprocessors, the 6809 provides two stacks (which may be anywhere in memory). U points to the top of the user stack, which is under the direct control of the user. S points to the top of the system stack, which is used in subroutine calls and interrupts (though it can be used by the programmer, too).

A and B are the accumulators. These registers are used for by the instructions which perform calculations. The A, and B registers can be viewed as a single 16-bit register D. A is the most significant byte of D, and B is the least.

DP is the direct page register. This register provides the most significant 8 bits of all addresses generated using a special direct page mode. This addressing mode is typically used when speed or code size is important.

CC is the condition code register. This register contains 8 different flag bits which either indicate processor status or control how the processor behaves. The bits in the CC are:

C: This is used to indicate that a carry or borrow was generated in the last operation.
V: This bit indicates that the last operation resulted in a signed arithmetic overflow.
Z: This bit indicates that the result of the last operation was a zero.
N: This bit indicates that the result of the last operation was a negative number (bit 7 is true).
I: When this bit is 1, interrupts requested on IRQ input will be ignored. The bit is set at system start-up and during interrupt processing.
H: Indicates if a carry was generated by the lower four bits of the addition. It is used by the DAA instruction.
F: When this bit is 1, interrupts requested on FIRQ input will be ignored. The bit is set at system start-up and during interrupt processing.
E: If 1, this register indicates that all registers were pushed onto the stack prior to jumping to the interrupt handler. If it is 0, only the PC and CC were pushed. This flag is used by the RTI instruction to restore the stack properly at the end of the interrupt handler.

Addressing Modes

There are numerous addressing modes on the 6809. Indeed, this is one of the chip's most attractive features. Most of the 8-bit processors from this era (the 6502, the 8080, the Z-80, and so on) had a much more limited set of addressing modes. Also, the 6809 is unique in its class in that the addressing modes are highly orthogonal. Many processors (class, can we say "Pentium?" I knew you could!) have addressing modes which only work for certain registers. Not so the 6809.

Inherent: This is the simplest mode. The operands are contained in registers, and it is part of the opcode which registers are to be used.
Immediate: This mode is for loading constants into registers. The value to be loaded is stored right after the opcode.
Extended: In this mode, the opcode is given a 16-bit address which points to a cell in memory.
Direct: This is like extended, except that the code only supplies the least significant 8 bits of the address---the most significant bits come from the DP register.
Constant Offset from Register: This is the first of the index addressing modes. A pointer register (X, Y, U, or S) is given along with some constant value. This constant is added to the contents of the pointer, and the result is the address of the cell to be accessed. The constant can be in a number of forms: it can be 0, it can be a 5-bit value, an 8-bit value, or a 16-bit value. The more bits used, the larger the range of cells you can access, but the longer the opcode is. Also, the constant is assumed to be a twos complement value.
Accumulator Offset from Register: This is like Constant Offset from Register except that the offset is in either A, B, or D.
Predecrement or Postincrement from Register: In this indexing mode, you can increment the pointer register (X, Y, U, or S) after you access the cell or you can decrement the pointer before you access it. This is like the ++ and -- operators in C. You can alter the pointer by either a byte (+ or -) or by a word (++ or --).
Program Counter Relative: This mode is just like Constant Offset from Register except that the offset is in either an 8 or 16 bit quantity, and the index register is the program counter.
Indirection: This adds a level of indirection to the indexing addressing mode used (it can be used with any of the four basic indexing modes). The word located at the address the indexing mode would normally generated is considered to be an address, and it is used to find the cell referenced. This is just like the indirect mode in the PDP-8.
Extended Indirection: This mode is indirection applied to the extended addressing mode.
Branch Relative: This is the addressing mode used in branches. A constant (either 8 or 16 bits long) is given. If the branch is to be taken, the constant is added to the program counter. Note that the constant is considered to be in two's complement.

Interrupts

All modern processors have some mechanism to allow peripherals or auxiliary circuitry to get the attention of the processor. Usually, there are tiers to the interrupts: there are usually several kinds of interrupts, with greater priority given to some interrupts than others. On the 6809 there are three tiers. Each of the three tiers corresponds to an interrupt input pin.

NMI: Non Maskable Interrupt. This kind of interrupt is for the most important (or most impatient) interrupts. The 6809 gives highest priority to NMIs.
FIRQ: Fast Interrupt Request. This is a mid-level interrupt. An NMI will interrupt a FIRQ, but a FIRQ can interrupt an IRQ. Also, a FIRQ only pushes the PC and the CC before going to the FIRQ handler.
IRQ: This is the lowest level interrupt. It can be interrupted by both NMIs and FIRQs. Also, IRQ pushes all the registers on the stack before going to the IRQ handler.